PURPOSE:To increase the fan-out of an integrated circuit device and also accelerate the operation thereof by employing a vertical SIT for switching and providing a P-N junction diode in parallel with the drain layer to isolate the respective output. CONSTITUTION:An N<->-type epitaxial layer 16 is formed on a P-type Si substrate 12 having an N<+>-type buried layer 14, is isolated with P<+>-type layers 18, and is used for the collector of a clamping bipolar transistor QB. The layer 16 is isolated with N<+>-type layers 20, a P<+>-type gate 22, a diode P<+>-type layers 24a-24c, and N<+>-type source 26 are selectively formed, and respective electrodes are attached thereto. The layers 14, 16 are the drains of the SIT, and with three diodes provided in parallel the drain output of the SIT is isolated. Since the vertical SITQW is used for switching according to this configuration, both the increase of the number of fan-out and the acceleration thereof become compatible, the voltage between the gate and the drain of the QS is clamped with the bipolar transistor QB, and the charge storage at the drain of the QS is reduced. In this manner, there is provided an SITL having low power consumption and high speed operation.