A bus error ascribable to a bus master module (2) other than a central processing unit (CPU) (1) is set as a specified factor for an exception process. When the exception process is requested, the CPU (1) executes a corresponding service program for the exception process without executing a process for altering and setting mask bits, which would be executed for a normal interrupt request. Thus, the exception process request specific to the bus error is not undesirably refused by interrupt requests etc., being accepted before the bus error. Furthermore there is a reduction in the time which is expended before the start of the run of a service program corresponding to the bus error, with the result that the reliability of the process for the bus error attributed to the predetermined bus master module (2) other than the CPU (1) is enhanced.




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